Fortran High-Level Synthesis: Reducing the barriers to accelerating HPC codes on FPGAs
by Gabriel Rodriguez-Canal, Nick Brown, Tim Dykes, Jessica R. Jones, and Utz-Uwe Haus
arXiv 25 Aug 2023
In recent years the use of FPGAs to accelerate scientific applications has grown, with numerous applications demonstrating the benefit of FPGAs for high performance workloads. However, whilst High Level Synthesis (HLS) has significantly lowered the barrier to entry in programming FPGAs by enabling programmers to use C++, a major challenge is that most often these codes are not originally written in C++. Instead, Fortran is the lingua franca of scientific computing and-so it requires a complex and time consuming initial step to convert into C++ even before considering the FPGA.
In this paper we describe work enabling Fortran for AMD Xilinx FPGAs by connecting the LLVM Flang front end to AMD Xilinx’s LLVM back end. This enables programmers to use Fortran as a first-class language for programming FPGAs, and as we demonstrate enjoy all the tuning and optimisation opportunities that HLS C++ provides. Furthermore, we demonstrate that certain language features of Fortran make it especially beneficial for programming FPGAs compared to C++. The result of this work is a lowering of the barrier to entry in using FPGAs for scientific computing, enabling programmers to leverage their existing codebase and language of choice on the FPGA directly.
Thank you for the interest in our work. We have just got aproval for the license on the HPE side and we will be releasing the code in the following days. There will be a bit more development after that in terms of tests and providing documentation, but it should be ready to play around with it soon.
I will be presenting Fortran-HLS at FPL 2023 on the 6th of September: Agenda. Happy to have a chat about the work if you happen to be there.
Thanks @gabrielrodcanal for the comment and welcome to the Discourse! Congratulations on the paper. We are always happy to see papers that use Fortran and @Beliavsky has been diligent in updating the whole Fortran community about such efforts.
I am one of the co-authors, so a bit biased , but I think this is nice as it enables us to make Fortran a first class citizen in terms of programming FPGAs. AMD Xilinx only support C/C++ with their tooling, and this is a pain because as an HPC developer if my code is in Fortran (which it very often is) then I need to undertake an initial and time consuming step of porting it to C++ before I get even anywhere near an FPGA. Furthermore, having two code bases can be a pain in terms of maintenance and the differences in array layout/indexing always gives me a headache too.
The work reported in this paper sits between Flang and AMD Xilinx’s HLS backend, effectively meaning that these are used unmodified to program FPGAs using Fortran with all the expressivity of AMD Xilinx’s C++ approach.
I suppose the only current limit is that AMD Xilinx are also undertaking lots of library development in C++ for FPGAs, as future work it would be nice to write Fortran bindings for these so that these can be called directly from Fortran codes - but I think those bindings (C style anyway) should be fairly easy to do.
As a general comment, as this is an FPGA conference we were a little worried that the reviewers might not see the benefit in providing Fortran programming for FPGAs, but they were all supportive in this regard and based on their comments it was clear that they can see the use that supporting Fortran for FPGAs can generally provide here.
Hi Nick and Gabriel,
welcome to Discourse and congratulations on the paper! Nice to hear the reviewers were supportive of Fortran.
Could you point us to a good introductory article on what FPGA’s can offer for HPC-style codes like PDE solvers or large linear algebra problems?
I can certainly imagine the benefit for typical kernels like stencil updates or tiled matrix multiplication. But how about branchy code, things like nonlinear property relations, complicated boundary conditions, etc., which often change considerably across problem domains? Do those pose any problems in terms of programming for an FPGA?
Not the authors but I expect FPGA would give amazing performance for things like FFT or other signal processing tasks.